Table of Contents
Chapter 6 -- Introduction to Sequential Devices
The Sequential Circuit Model
State Tables and State Diagrams
Sequential Circuit Example
Latch and Flip-flop Timing
TTL Memory Elements
Set Latch
Reset Latch
Set-Reset Latch (SR latch)
NAND SR Latch
Set-Reset Latch Timing Diagram
SR Latch Propagation Delays
SR Latch Characteristics
SN74279 Latch with Two Set Inputs
Gated SR Latch
Gated SR Latch Characteristics
Delay Latch (D latch)
D Latch Characteristics
D Latch Timing Diagram
D Latch Timing Constraints
The SN74LS75 D Latch
Propagation Delays and Time Constraints for the SN74LS75
Hazard-Free D Latch, the SN74116
Master-Slave SR Flip-flop
SR Master-Slave Flip-Flop Characteristics
Master-Slave D Flip-Flop
Master-Slave D Flip-Flop Characteristics
Pulse-Triggered JK Flip-Flop Characteristics
Pulse-Triggered JK Flip Realization
The SN7476 Dual Pulse-Triggered JK Flip-Flop
SN7474 Dual Positive-Edge-Triggered D Flip-Flop
SN7474 Excitation Table
SN7474 Flip-Flop Timing Specifications
SN74175 Positive-Edge-Triggered D Flip-Flop
SN74273 Positive-Edge-Triggered D Flip-Flop
SN74LS73A Edge-Triggered JK Flip-Flop Logic Diagram
SN74LS73A Logic Symbols
SN74276 and SN74111 Edge-Triggered JK Flip-Flops
Negative-Edge-Triggered T Flip-Flop
Edge-Triggered T Flip-Flop Characteristics
Clocked T Flip-Flop
Excitation Table for Clocked T Flip-Flops
The Clocked T Flip-Flop Timing Diagram
Summary of Latch and Flip-Flop Characteristics
SE555 Precision Timing Module
Astable Operation of The SE555
Monostable (One shot) Device Realization
PROM-based Sequential Circuits
PROM-based Sequential Circuit Example
Prime Number Sequencer
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