Timing Hazards in Combinational Logic Circuits
Hazards are undesirable changes in the output of a combinational logic circuit caused by unequal gate propagation delays.
Static hazard (glitch) -- the output momentarily changes from the correct or static state
- Static 1 hazard -- the output changes from 1 to 0 and back to 1
- Static 0 hazard -- the output changes from 0 to 1 and back to 0
Dynamic hazard (bounce) -- the output changes multiple times during a change of state
- Dynamic 0 to 1 hazard -- the output changes from 0 to 1 to 0 to 1
- Dynamic 1 to 0 hazard -- the output changes from 1 to 0 to 1 to 0