Table of Contents
Chapter 8 -- Analysis and Synthesis of Synchronous Sequential Circuits
The Synchronous Sequential Circuit Model
Mealy Machine Model
Mealy Machine Timing Diagram -- Example 8.1
Moore Machine Model
Moore Machine Timing Diagram -- Example 8.2
Analysis of Sequential Circuit State Diagrams -- Example 8.3
Timing Diagram for Example 8.3
Analysis of Sequential Circuit Logic Diagrams
Timing Diagram for Figure 8.8 (a)
State Table and State Diagram for Figure 8.8 (a)
K-Maps for Circuit of Figure 8.8 (a)
Synchronous Sequential Circuit with T Flip-Flop -- Example 8.4
Timing Diagram for Example 8.4
State Table and State Diagram for Example 8.4
K-Maps for Example 8.4
Synchronous Sequential Circuit with JK Flip-flops -- Example 8.5
Timing Diagram and State Table for Example 8.5
K-Maps for Example 8.5
Generating the State Table From K-maps -- Example 8.5
Synchronous Sequential Circuit Synthesis
Introductory Synthesis Example -- Example 8.6
Flip-flop Input Tables -- Example 8.6
Generating the JK Flip-flop Excitation Maps -- Example 8.7
Clocked JK Flip-Flop Implementation -- Example 8.7
Application Equation Method for Deriving Excitation Equations -- Example 8.8
Sequence Recognizer for 01 Sequence -- Example 8.9
Synthesis of the 01 Recognizer with SR Flip-flops
Realization of 01 Recognizer with T Flip-flops
Design of a Recognizer for the Sequence 1111 -- Example 8.11
SR Realization of the 1111 Recognizer
Clocked T and JK Realizations of the 1111 Recognizer
Clocked JK Flip-Flop Realization of a 1111 Recognizer
Design of a 0010 Recognizer
Design of a Serial Binary Adder
Design of a Four-State Up/Down Counter
An Implementation of the Up/Down Counter
Design a BCD Counter
Design of the BCD Counter (con’t)
Realization of the BCD Counter Design
K-map For Y1 in Example 8.16
Robot Controller Floor Plan -- Example 8.17
Robot Controller Design
Robot Controller Realization
Candy Machine Controller Design -- Example 8.18
Algorithmic State Machines (ASMs)
ASM Representation of a Mealy Machine
ASM Representation of a Moore Machine
Eight-Bit Two’s Complementer ASM -- Example 8.19
Binary Multiplier Controller -- Example 8.20
One-Hot State Assignments
ASM Design Using One-Hot State Assignments
ASM Design Using One-Hot Assignments (con’t)
One-hot Design of A Multiplier Controller -- Example 8.21
Incompletely Specified Circuits -- Detonator (Example 8.22)
Detonator Example K-maps
Detonator Realization
Sate Assignments and Circuit Realization
CAD Formatted Truth Table
VHDL Description of a Sequential Circuit
State Assignment Options in AutoLogic
VHDL Generated Design Example
Propagation Delays in a Sequential Circuit
Sequential Circuit Timing Constraints
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