CSE 2441/5440

CSE 2341 DIGITAL LOGIC CIRCUITS SPRING 1999 (1/25/99)

COURSE OBJECTIVES

To introduce the basic concepts and methods needed to analyze, design, build, and test combinational, synchronous, and asynchronous sequential logic circuits with SSI, MSI, and LSI integrated circuits.

INSTRUCTOR

            Bill Carroll, CSE Professor and Chairperson
            Office: 320 Nedderman Hall
            Office hours: TTh 1:30 to 3:00 PM, W 9:00 to 10:30 AM, or by appointment
            Phone: (817) 272-3787
            Email: carroll@cse.uta.edu

LABORATORY INSTRUCTORS and GRADER

            Jayendra (Jay) Gowrishankar                                                             Masud Khan
            Office: 250 NH                                                                                 Office: 247 NH
            Office Hours: 11:00 AM - 12 NOON, TTh                                       Office Hours: 3:00 - 4:00 PM, TTh
            Phone: (817)272-5458                                                                      Phone: (817)272-2957
            Email: gowrisha@cse.uta.edu                                                             Email: khan@cse.uta.edu

TIME AND PLACE

Lecture Section 001 – MW 1:00 TO 1:50 PM, 110 Nedderman Hall (NH)
Laboratory Section 301 – M 3:30 to 6:20 PM, 122 NH [Jay]
Section 302 – T 3:30 to 6:20 PM, 122 NH [Jay]
Section 303 – W 10:00 AM to 12:50 PM, 122 NH [Masud] PREREQUISITES – CSE 2312, CSE 2315, and EE 2320 or equivalent

TEXTBOOKS

V. P. Nelson, H. T. Nagle, B. D. Carroll, and J. D. Irwin Digital Logic Circuit Analysis & Design, Prentice-Hall, 1995.
Capilano Computing Systems, Ltd., LogicWorks3, Addison-Wesley, 1996.

HANDOUTS will be placed on the web at http://www-cse.uta.edu/~carroll/cse2341

GRADING

Final grades will be assigned according to the following scale.

                        A: 100 ³ Average ³ 90
                        B: 90 > Average ³ 80
                        C: 80 > Average ³ 70
                        D: 70 > Average ³ 60
                        F: 60 > Average

where Average = 0.20*Exam1 + 0.20*Exam2 + 0.30*FinalExam + 0.20 *(Lab average) + 0.10*(Homework average).

EXAMINATIONS

There will be three examinations including the final examination. See the schedule below for the dates. Missed examinations can be "made up" within one week of the date of the examination if sufficient justification for missing can be given. Examinations are closed book and closed notes, and the final exam is not comprehensive.

HOMEWORK AND QUIZZES

Homework will typically be assigned and collected on a weekly basis. Selected problems will be graded on each assignment. Solutions will be provided in the Fast Copy Center after the due date. Some homework assignments may involve solving problems on the computer in a programming language of your choice or with LogicWorks. All assignments requiring computer use will be graded. Late homework papers will not be accepted. Quizzes will occasionally be given on days that homework is due. Missed quizzes cannot be "made up."

LABORATORY

Laboratories begin the second week of class. The laboratory will include an introductory session, nine laboratory assignments, and a laboratory quiz. Please see the schedule below for the dates. If you miss a lab or cannot finish a lab during the designated lab week(s), you may "make up" or finish the lab during one of two makeup weeks (see the schedule below). However, there is 20% penalty unless it was caused by an emergency and prearranged with the lab instructor.

POLICIES

1. Attendance is expected and will be checked each period. Students having three or more unexcused absences will have their final average reduced by ten points before their final letter grade is assigned.

2. You are expected to have read the assigned readings by the specified dates. Lectures will review and augment the material in the textbook.

3. Late homework will not be accepted.

4. Cheating in any form will not be tolerated. Anyone suspected of cheating will be dealt with according to applicable UTA policies and procedures. It is your responsibility to know University policies on these matters. Sharing your work with another student, even temporarily, is collusion. Copying work from a tutor or solutions from previous semesters is plagiarism. Students will be expected to read and sign the College of Engineering Statement of Ethics.

5. If you require an accommodation based on disability, I would like to meet with you in the privacy of my office the first week of the semester to be sure you are appropriately accommodated.

Class/Lab Schedule* (1/20/99)

Week	Monday Class Date	Reading (Chapters.sections)	Lecture Topic	Lab	Important Information
1	1/20(Wed)	0	Course overview. Intro to digital systems.	No lab
2	1/25	1	Number systems and codes.	Lab Intro.
3	2/1	1, 2.1-2.2	Codes. Boolean algebra.	Lab 1	Census day (2/3)
4	2/8	2.3-2.6	Combinational logic circuits.	Lab 2
5	2/15	3.1-3.6	Function simplification. K maps.	Lab 3
6	2/22	3.7, 4.1-4.2,4.4,4.6	Incompletely specified functions. Decoders, encoders, multiplexers.	Lab 4	Last day to drop with W if failing (2/26)
7	3/1	4.8	Arithmetic/logic circuits.	Makeup	*Exam 1 -- 3/3*
8	3/8	6.1-6.4	Sequential circuits, latches, flip flops.	Lab 5	Mid semester (3/12)
9	3/15		*Spring break.*
10	3/22	8.1-8.2	Mealy and Moore machines. Analysis.	Lab 6
11	3/29	8.3	Sequential circuit synthesis.	Lab 7
12	4/5	8.4,7.1	ASMs. Register modules.	Lab 8	*Exam 2 -- 4/7*
13	4/12	7.2-7.5	Counter modules.	Lab 9	Last day to drop (4/16)
14	4/19	9.1-9.3	State table reduction.	Lab 9 (ctd)
15	4/26	9.4	Optimal state assignments.	Makeup
16	5/3	Review	Catch up and problem sessions.	Lab Quiz
17	5/10		Final exam covers chapters 7 and 9 plus problems from exams 1 and 2.		*Final Exam* *(11:00 AM until 1:30 PM)*

* Subject to change. If changes are necessary, they will be reflected on the web version only.