Table of Contents
Chapter 6 -- Introduction to Sequential Devices
The Sequential Circuit Model
State Tables and State Diagrams
Sequential Circuit Example
TTL Memory Elements
SR Latch Characteristics
Latch and Flip-flop Timing
Set Latch
Reset Latch
Set-Reset Latch (SR latch)
NAND SR Latch
Set-Reset Latch Timing Diagram
SR Latch Propagation Delays
SN74279 Latch with Two Set Inputs
Gated SR Latch
Gated SR Latch Characteristics
Delay Latch (D latch)
D Latch Characteristics
D Latch Timing Diagram
D Latch Timing Constraints
Pulse-Triggered JK Flip-Flop Characteristics
Pulse-Triggered JK Flip Realization
The SN7476 Dual Pulse-Triggered JK Flip-Flop
SN7474 Dual Positive-Edge-Triggered D Flip-Flop
SN7474 Excitation Table
SN7474 Flip-Flop Timing Specifications
Summary of Latch and Flip-Flop Characteristics
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