CSE 2341                                                                                 DIGITAL LOGIC CIRCUITS                                                                      SUMMER 1999

(6/1/99)

COURSE OBJECTIVES

         To introduce the basic concepts and methods needed to analyze, design, build, and test combinational, synchronous, and asynchronous sequential logic circuits with SSI, MSI, and LSI integrated circuits.

INSTRUCTOR

        Bill Carroll, CSE Professor and Chairperson
        Office: 320 Nedderman Hall
        Office hours: TTh 2:00 to 3:00 PM, W 10:30 to 11:30 AM, or by appointment
        Phone: (817) 272-3787
        Email: carroll@cse.uta.edu

LABORATORY INSTRUCTORS and GRADER

        Masud Khan                                                                     Hossain Rahman
        Office: 247 NH                                                                  Office: 247 NH
        Office Hours: T 2:00 to 3:30, Th 2:00 to 3:00 PM                 Office Hours: MW 3:30 to 5:00 PM
        Phone: (817) 272-3607                                                      Phone: (817) 272-3607
        Email: khan@cse.uta.edu                                                 Email: rahman@cse.uta.edu

TIME AND PLACE

        Lecture Section 601 – TTh 3:30 TO 4:50 PM, 110 Nedderman Hall (NH)
        Laboratory Section 801 – T 5:30 to 8:20 PM, 122 NH
        Section 802 – W 5:30 to 8:20 PM, 122 NH

PREREQUISITES – CSE 2312, CSE 2315, and EE 2320 or equivalent

TEXTBOOKS

        V. P. Nelson, H. T. Nagle, B. D. Carroll, and J. D. Irwin Digital Logic Circuit Analysis & Design, Prentice-Hall, 1995.
        Capilano Computing Systems, Ltd., LogicWorks3, Addison-Wesley, 1996.

HANDOUTS will be placed on the web at http://www-cse.uta.edu/~carroll/cse2341/summer99

GRADING

        Final letter grades will be assigned according to the following scale.

                A: 100 ³ Grade ³ 90
                B: 90 > Grade ³ 80
                C: 80 > Grade ³ 70
                D: 70 > Grade ³ 60
                F: 60 > Grade

where Grade = 0.30*MidTermExam + 0.30*FinalExam + 0.25 *(Lab average) + 0.15*(Homework average).

EXAMINATIONS

        There will be two examinations including the final examination. See the schedule below for the dates. Missed examinations can be "made up" within one week of the date of the examination if sufficient justification for missing can be given. Examinations are closed book and closed notes, and the final exam is semi-comprehensive.

HOMEWORK AND QUIZZES

        Homework will typically be assigned and collected on a weekly basis. Selected problems will be graded on each assignment. Solutions will be provided in the Fast Copy Center after the due date. Some homework assignments may involve solving problems on the computer in a programming language of your choice or with LogicWorks. All assignments requiring computer use will be graded. Late homework papers will not be accepted. Quizzes will occasionally be given on days that homework is due. Missed quizzes cannot be "made up."

LABORATORY

        Laboratories begin the first week of class. The laboratory will include an introductory session, and eight laboratory assignments. Please see the schedule below for the dates. If you miss a lab or cannot finish a lab during the designated lab week(s), you may "make up" or finish the lab during one of two makeup weeks (see the schedule below). However, there is 20% penalty unless it was caused by an emergency and prearranged with the lab instructor.

POLICIES

        1. Attendance is expected and will be checked each period. Students having three or more unexcused absences will have their final average reduced by ten points before their final letter grade is assigned.
        2. You are expected to have read the assigned readings by the specified dates. Lectures will review and augment the material in the textbook.
        3. Late homework will not be accepted.
        4. Cheating in any form will not be tolerated. Anyone suspected of cheating will be dealt with according to applicable UTA policies and procedures. It is your responsibility to know University policies on these matters. Sharing your work with another student, even temporarily, is collusion. Copying work from a tutor or solutions from previous semesters is plagiarism. Students will be expected to read and sign the College of Engineering Statement of Ethics.
        5. If you require an accommodation based on disability, I would like to meet with you in the privacy of my office the first week of the semester to be sure you are appropriately accommodated.
 
 

Class/Lab Schedule* (6/1/99)


 
Week 
Tuesday Class Date
Reading

(Chapters.sections)

Lecture Topic
Lab
Important Information
1
6/1
0,1
Course overview. Intro to digital systems. Number systems and codes. 
Lab Intro
Census day (6/7)
2
6/8
2.1-2.6
Boolean algebra. 

Combinational logic circuits.

Lab 1
 
3
6/15
3.1-3.7
Function simplification. K maps.

Incompletely specified functions.

Lab 2
 
4
6/22
4.1-4.2, 4.4, 4.6, 4.8
Decoders, encoders, multiplexers.

Arithmetic/logic circuits.

Lab 3
Last day to drop with W if failing (6/28)
5
6/29
 
Catch up and review.
Makeup
Mid-term Exam – 7/1
6
7/6
6.1-6.4
Sequential circuits, latches, flip flops.
Lab 4
 
7
7/13
8.1-8.3
Sequential circuit analysis and synthesis. Mealy and Moore machines. 
Lab 5
 
8
7/20
8.4
Algorithmic state machines.
Lab 6
Last day to drop (7/26)
9
7/27
7.1-7.5
Register modules. Counter modules.
Lab 7
 
10
8/3
9.1-9.3
State table reduction.
Lab 8
 
11
8/10
 
Final exam is semi-comprehensive.
Makeup
Final Exam

* Subject to change. If changes are necessary, they will be reflected on the web version only.