Table of Contents
Chapter 6 -- Introduction to Sequential Devices
The Sequential Circuit Model
Models for Sequential Circuits
State Tables and State Diagrams
Example 6.1 State tables and Diagrams
Example 6.1 (continued)
Example sequential circuit
Memory Devices
Table 6.1 TTL Memory Elements [1]
Set-reset latch
NAND SR Latch
SR Latch Timing Diagrams
Set-Reset Latch Timing Diagram
Delay Parameters
Delay Parameters (continued)
SR Latch Propagation Delays
SR Latch Excitation Table and Characteristic Equation
SR Latch: Characteristic Equation (continued)
SR latch characteristics
Gated SR Latch
Gated SR Latch (continued)
Gated SR Latch
Gated SR Latch (continued)
Gated SR Latch Characteristics
Delay Latch
Delay Latch (D latch)
D Latch Characteristics
D Latch (continued)
D Latch Timing Diagram
D Latch (continued)
D Latch (continued)
D Latch Timing Constraints
Flip-Flops
Master-Slave SR Flip-Flops
Master-Slave SR Flip-Flops (continued)
Master-slave SR flip-flop
PPT Slide
Excitation Table and Characteristic Equation
SR Master-Slave Flip-Flop Characteristics
Master-Slave D Flip-Flops
Master-Slave D Flip-Flop
PPT Slide
Master-Slave JK Flip-Flops
PPT Slide
JK Flip-Flops (continued)
Pulse-Triggered JK Flip-Flop Realization
7476 Dual Pulse-triggered JK Flip-Flop Module
The SN7476 Dual Pulse-Triggered JK Flip-Flop
Edge-triggered D Flip-Flops
7474 Dual Positive-edge-triggered D Flip-Flop Module
PPT Slide
SN7474 Excitation Table
Edge-triggered Flip-flop Timing Characteristics
PPT Slide
T Flip-flops
Negative-Edge-Triggered T Flip-Flop
Edge-Triggered T Flip-Flop Characteristics
Clocked T Flip-flops
Clocked T Flip-Flop
Excitation Table for Clocked T Flip-Flops
PPT Slide
Table 6.3 Summary of Latch and Flip-Flop Characteristics
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