Table 6.1TTL Memory Elements [1]

Device Elements Element Description

Number of

74LS73A

7474

74LS75

7476

74111

74116

74175

74273

74276

74279

2

2

4

2

2

2

4

8

4

4

Negative-edge triggered flip-flop with clear

Positive-edge triggered D flip-flop with preset and clear

D latch with enable

Pulse-triggered JK flip-flop with preset and clear

Master-slave JK flip-flop with preset, clear, data lockout

4-Bit hazard-free D latch with clear and dual enable

Positive-edge triggered D flip-flop with clear

Positive-edge triggered D flip-flop with clear

Negative-edge triggered JK flip-flop with preset, clear

SR latch with active-low inputs

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