D Latch (continued)
is defined as the period of time immediately following the enable signal transition during which D should not change. Therefore, the excitation input must be held constant for at least th following the enable signal transition to ensure the correct value has been latched.
Setup and hold times are illustrated in Fig. 6.18
Note the two constraint violations:
- the change in D from 0 to 1 too close to the clock edge represents a setup time violation
- the change in D from 1 to 0 too soon after the clock edge may result in an unpredictable state.