Master-Slave D Flip-Flops
A master-slave D flip-flop can be built from two D latches as shown in Fig. 6.23a.
This flip-flop operates in the same manner as the SR version; the master latch is gated when the clock is low and the slave, when the clock is high.
The logic symbol for this pulse-triggered device indicates that the outputs change on the positive edge of a pulse on the clock signal (Fig. 6.23b).
The overall behavior of the D flip-flop output Q can be summarized by noting that Q will assume the value of D on the rising edge of the clock C.
Therefore, the characteristic equation for a master-slave D flip-flop is : Q* = D