7476 Dual Pulse-triggered JK Flip-Flop Module
Figure 6.27 shows the logic symbol of the SN7476. This device packages two flip-flops that operate in the manner displayed in Fig. 6.26.
Included in the configuration are asynchronous set signals PRE and reset signals CLR. The PRE and CLR signals override the operation of the pulse-triggered inputs J, K and CLK.
This means that if CLR = 0 then the state Q* goes to 0, or if PRE = 0 the state Q* sets to 1, independent of the values of the clock and the excitation inputs.