Spring 2008 Final Exam Review Page

CSE2340                                                                                                                                                                                            Dr. Tiernan

Final exam is comprehensive. This sheet lists topics to be included on the Final beyond those of Test #2. See Test #1 and #2 Review pages for reminders about important topics from that material.

Test will be open book.                                                          Final is Tuesday May 6^th at 2pm in class.

 

Topics to understand and be able to use:

Synthesis of completely specified sequential circuits

State assignment

Redundant states and why to reduce

                  State equivalence;

                  Equivalence classes and compatibility classes

State reduction

                  by inspection

                  by partitioning

                  by the implication table

Maximal compatibility classes

Merger diagrams

Upper and lower bounds of states in minimal circuit

Number of possible state assignments (p. 605)

Criteria for optimal state assignment (P. 619)

 

Topics to be familiar with but not to apply:

Rules for optimal state assignment

 

Topics to understand and be able to use from earlier in semester:

Full- adder (equations and diagram)

Combinational vs. Sequential logic

State diagrams and state tables

Circuit behavior (as a table – see Ex. 6.1)

Timing diagrams

SR, D, JK, T edge-triggered flip-flops

Analysis of state diagrams and logic diagrams (for synchronous circuits)

Be able to reduce/ simplify functions using Boolean algebra

Meaning and use of

                  POS, SOP, canonical POS/SOP, minimum POS/SOP

                  maxterms, minterms

Truth tables

AND, OR, NOT gates

NAND, NOR gates

                  how these gates can be used in place of AND, OR, NOT

Karnaugh maps

Timing delay and propogation

Encoder / Decoder

Multiplexer / Demux

 

Test will have some or all of the following characteristics:

                  multiple choice questions (not more than 10) – typically 1 to 2 points each

                  short answer question

                  design synthesis questions

                  design analysis questions

 

Some questions will be linked in sequence. Answer as much as you can even if you have to skip a question and then guess at where to start the next question.

 

Document any assumption you make.

 

Questions generally have their point value listed in braces at the end/side of the question

Every test will have at least 10 points worth of extra credit available