Delay Latch
When storing data, a memory element’s excitation input is simply the data to be stored.
A device (which is called a delay latch or D latch) is needed that transfers a logic value on its excitation input D into the cross-coupled storage cell of a latch.
The logic symbol of the D latch is shown in Fig. 6.15a. Such a device can be created from a gated SR latch, by assigning S = D and R = D.
The D latch excitation table and state diagram is shown in Figs. 6.16 a and b.
A NAND implementation of the D latch is shown in 6.15b and NOR is shown in 6.15c.