Edge-triggered D Flip-Flops
All the pulse-triggered flip-flops discussed previously, require both a rising and falling edge on the clock for proper operation.
Another approach is to design the flip-flop circuitry so that it is sensitive to its excitation inputs only during rising or falling transitions of the clock.
A circuit with this design is called positive edge triggered if it responds to a 0 to 1 clock transition, or negative edge triggered if it responds to a 1 to 0 clock transition.
The edge-sensitive feature eliminates unstable transients by drastically reducing the period during which the input excitation signals are applied to the internal latches.