7474 Dual Positive-edge-triggered D Flip-Flop Module
Fig. 6.28b presents the logic symbol for the SN7474. It is important to note that the small triangle at the C1 input to the device is the standard notation to indicate that it is positive edge triggered.
The modes of operation are shown in the excitation table of Fig. 6.29. Note that the asynchronous preset and clear signals override the clocked operation of the circuit.
When both CLR and PRE are inactive (high), the clock, CLK, takes control of the device.
While CLK is low, the flip-flop is in the hold mode. However, on a 0 to 1 transition of the clock the data input D is transferred to the flip-flop output Q.