SR Latch Timing Diagrams
The operation of any latch circuit may be described using a timing diagram.
The diagram shown in Fig. 6.9 shows that placing logic 1 signals on both the R and S inputs forces both outputs, Q and Q, to logic 0.
When the two inputs are returned to logic 0, a race condition is created, and which state the device will assume can not be determined.
Consequently, the use of the SR latch is restricted to exclude the input combination S = R = 1.
If the R signal is returned to logic 0 before S, the final state of Q will be a logic 1. If S is returned to logic 0 first, the device will be reset to logic 0.