Master-Slave SR Flip-Flops
One method to prevent unstable behavior is to employ two latches in a master-slave configuration as shown in Fig. 6.21a.
When the clock signal C is low, the master latch is in the gated mode and slave is in the hold mode. Changes on the excitation input signal S and R are gated into the master latch while the slave latch ignores any changes on its inputs.
When the clock changes to logic 1, the two latches exchange roles. The slave latch enters the gated mode, sending the output of the master latch to the flip-flop output Q, while the master latch enters the hold mode.