Master-Slave SR Flip-Flops (continued)
Master-slave flip-flops are sometimes called pulse triggered because they require both logic 0 to 1 and 1 to 0 transitions on the clock input in order to operate properly.
The logic symbol of Fig. 6.21b indicates the pulse-triggered nature of the device by showing the clock edge transition that enables the slave at the flip-flop output terminals Q and Q.
In Fig. 6.21b, the rising transition indicates that the flip-flop outputs change on the positive edge of a pulse on the clock signal.
If the SR flip-flop is used in a synchronous sequential circuit, an unstable oscillation cannot occur because, at all times, either the master or the slave latch is in the hold mode (Fig. 6.21d).